1.?MSEE/CE?
2.?Strong?analytical,?and?problem?solving?skills?as?well?as?hands-on?lab?debugging?skills?
3.?Good?knowledge?of?RTL?simulation?and?synthesis.?Knowledge?of?design?for?low?power?and?design?for?test?(DFT)?
4.?Any?of?the?following?skills?&?experience?is?highly?desirable,?but?NOT?required:
(a).?able?to?write?C?code?to?model?RTL?blocks?for?simulation?and?verification.
(b).?able?to?write?reusable?Verilog?RTL?codes,?follow?design?and?DFT?guidelines.
(c).?able?to?run?synthesis,?static?timing?analysis?and?formal?verification.
(d).?knowledge?in?languages?relevant?to?the?ASIC?development?process?including?Verilog,?UNIX?scripting,?Perl?and?Tcl?is?strong?plus.
5.?DSP?function?implementation?experience?is?a?plus.
6.?Self-motivated,?excellent?communication?skills?and?ability?to?excel?in?a?team?environment
